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1. general description the pca9535a is a low-voltage 16-bit genera l purpose input/output (gpio) expander with interrupt and reset for i 2 c-bus/smbus applications. nxp i/o expanders provide a simple solution when additional i/os are needed while keeping interconnections to a minimum, for example, in acpi power switch es, sensors, push buttons , leds, fan control, etc. in addition to providing a flexible set of gpios, the wide v dd range of 1.65 v to 5.5 v allows the pca9535a to interface with next-generation microprocessors and microcontrollers where supply levels are dropping down to conserve power. the pca9535a contains the pca9535 register set of four pairs of 8-bit configuration, input, output, and polarity inversion registers. the pca9535a is a pin-to-pin replacement to the pca9535 and other industry-standard devices. a more fully featured device, the pcal9535a, is available with agile i/o features. see the respective data sheet for more details. the pca9535a open-drain interrupt (int ) output is activated when any input state differs from its corresponding input port register st ate and is used to indicate to the system master that an input state has changed. int can be connected to the interrupt input of a microcontroller. by sending an interrupt signal on this line, the remote i/o can inform the microcontroller if there is incoming data on its ports without having to communicate via the i 2 c-bus. thus, the pca9535a can remain a simple slave device. the device outputs have 25 ma sink capabilitie s for directly driving leds while consuming low device current. the power-on reset sets the registers to their default values and initializes the device state machine. three hardware pins (a0, a1, a2) select the fixed i 2 c-bus address and allow up to eight devices to share the same i 2 c-bus/smbus. 2. features and benefits ? i 2 c-bus to parallel port expander ? pin and function compatible with pca9535 ? operating power supply voltage range of 1.65 v to 5.5 v pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt rev. 1 ? 11 september 2012 product data sheet
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 2 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt ? low standby current consumption: ? 1.5 ? a (typical at 5 v v dd ) ? 1.0 ? a (typical at 3.3 v v dd ) ? schmitt-trigger action allows slow input tran sition and better switching noise immunity at the scl and sda inputs ? v hys = 0.10 ? v dd (typical) ? 5 v tolerant i/os ? open-drain active low interrupt output (int ) ? 400 khz fast-mode i 2 c-bus ? internal power-on reset ? power-up with all channels configured as inputs ? no glitch on power-up ? latched outputs with 25 ma drive maximu m capability for directly driving leds ? latch-up performance exceeds 100 ma per jesd78, class ii ? esd protection exceeds jesd22 ? 2000 v human body model (a114-a) ? 1000 v charged-device model (c101) ? packages offered: tssop24, hwqfn24 3. ordering information 3.1 ordering options table 1. ordering information type number package name description version pca9535ahf hwqfn24 plastic thermal enhanced ve ry very thin quad flat package; no leads; 24 terminals; body 4 ? 4 ? 0.75 mm sot994-1 PCA9535APW tssop24 plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 table 2. ordering options type number topside mark temperature range pca9535ahf 535a ? 40 ? c to +85 ?c PCA9535APW pca9535a ? 40 ? c to +85 ?c
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 3 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 4. block diagram 5. pinning information 5.1 pinning remark: all i/os are set to inputs at reset. fig 1. block diagram of pca9535a pca9535a power-on reset 002aag207 i 2 c-bus/smbus control input filter scl sda v dd input/ output ports p0_0 v ss 8-bit write pulse read pulse p0_2 p0_1 p0_3 p0_4 p0_5 p0_6 p0_7 input/ output ports p1_0 8-bit write pulse read pulse p1_2 p1_1 p1_3 p1_4 p1_5 p1_6 p1_7 a1 a0 lp filter v dd int a2 fig 2. pin configuration for tssop24 fig 3. pin configuration for hwqfn24 v dd sda scl a0 p1_7 p1_6 p1_5 p1_4 p1_3 p1_2 p1_1 p1_0 int a1 a2 p0_0 p0_1 p0_2 p0_3 p0_4 p0_5 p0_6 p0_7 v ss PCA9535APW 002aag208 1 2 3 4 5 6 7 8 9 10 11 12 14 13 16 15 18 17 20 19 22 21 24 23 002aag209 transparent top view p1_3 p0_4 p0_5 p1_4 p0_3 p1_5 p0_2 p1_6 p0_1 p1_7 p0_0 a0 p0_6 p0_7 v ss p1_0 p1_1 p1_2 a2 a1 int v dd sda scl terminal 1 index area 6 13 5 14 4 15 3 16 2 17 1 18 7 8 9 10 11 12 24 23 22 21 20 19 pca9535ahf
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 4 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 5.2 pin description [1] hwqfn24 package die supply ground is connected to both v ss pin and exposed center pad. v ss pin must be connected to supply ground for pr oper device operation. for enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias need to be incorporated in the pcb in the thermal pad region. [2] pins p0_0 to p0_7 correspond to bits p0.0 to p0.7. at power-up, all i/o are configured as high-impedance inputs. [3] pins p1_0 to p1_7 correspond to bits p1.0 to p1.7. at power-up, all i/o are configured as high-impedance inputs. table 3. pin description symbol pin type description tssop24 hwqfn24 int 1 22 o interrupt output. connect to v dd through a pull-up resistor. a1 2 23 i address input 1. connect directly to v dd or v ss . a2 3 24 i address input 2. connect directly to v dd or v ss . p0_0 [2] 4 1 i/o port 0 input/output 0. p0_1 [2] 5 2 i/o port 0 input/output 1. p0_2 [2] 6 3 i/o port 0 input/output 2. p0_3 [2] 7 4 i/o port 0 input/output 3. p0_4 [2] 8 5 i/o port 0 input/output 4. p0_5 [2] 9 6 i/o port 0 input/output 5. p0_6 [2] 10 7 i/o port 0 input/output 6. p0_7 [2] 11 8 i/o port 0 input/output 7. v ss 12 9 [1] power ground. p1_0 [3] 13 10 i/o port 1 input/output 0. p1_1 [3] 14 11 i/o port 1 input/output 1. p1_2 [3] 15 12 i/o port 1 input/output 2. p1_3 [3] 16 13 i/o port 1 input/output 3. p1_4 [3] 17 14 i/o port 1 input/output 4. p1_5 [3] 18 15 i/o port 1 input/output 5. p1_6 [3] 19 16 i/o port 1 input/output 6. p1_7 [3] 20 17 i/o port 1 input/output 7. a0 21 18 i address input 0. connect directly to v dd or v ss . scl 22 19 i serial clock bus. connect to v dd through a pull-up resistor. sda 23 20 i/o serial data bus. connect to v dd through a pull-up resistor. v dd 24 21 power supply voltage.
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 5 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 6. functional description refer to figure 1 ? block diagram of pca9535a ? . 6.1 device address a2, a1 and a0 are the hardware address package pins and are held to either high (logic 1) or low (logic 0) to assign one of the eight possible slave addresses. the last bit of the slave address (r/w ) defines the operation (read or write) to be performed. a high (logic 1) selects a read operation, while a low (logic 0) selects a write operation. 6.2 registers 6.2.1 pointer register and command byte following the successful acknowledgement of the address byte, the bus master sends a command byte, which is stored in the pointer register in the pca9535a. the lower three bits of this data byte state the operatio n (read or write) and the internal registers (input, output, polarity inversion, or configurat ion) that will be affe cted. this register is write only. [1] undefined. fig 4. pca9535a device address r/w 002aah371 0 1 0 0 a2 a1 a0 hardware selectable slave address fixed fig 5. pointer register bits 002aaf540 b7 b6 b5 b4 b3 b2 b1 b0 table 4. command byte pointer register bits command byte (hexadecimal) register protocol power-up default b7 b6 b5 b4 b3 b2 b1 b0 0 0 0 0 0 0 0 0 00h input port 0 read byte xxxx xxxx [1] 0 0 0 0 0 0 0 1 01h input port 1 read byte xxxx xxxx 0 0 0 0 0 0 1 0 02h output port 0 read/write byte 1111 1111 0 0 0 0 0 0 1 1 03h output port 1 read/write byte 1111 1111 0 0 0 0 0 1 0 0 04h polarity inversion port 0 read/write byte 0000 0000 0 0 0 0 0 1 0 1 05h polarity inversion port 1 read/write byte 0000 0000 0 0 0 0 0 1 1 0 06h configuration port 0 read/write byte 1111 1111 0 0 0 0 0 1 1 1 07h configuration port 1 read/write byte 1111 1111
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 6 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 6.2.2 input port register pair (00h, 01h) the input port registers (registers 0 and 1) reflect the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by the configuration register. the input port registers are read only ; writes to these registers have no effect. the default value ?x? is determined by the externally applied logic level. an input port register read operation is performed as described in section 7.2 ? reading the port registers ? . 6.2.3 output port register pair (02h, 03h) the output port registers (registers 2 and 3) show the outgoing logic levels of the pins defined as outputs by the configuration register. bit values in these registers have no effect on pins defined as inputs. in turn, reads from these registers reflect the value that was written to these registers, not the actual pin value. a register pair write is described in section 7.1 and a register pair read is described in section 7.2 . table 5. input port 0 register (address 00h) bit 7 6 5 4 3 2 1 0 symbol i0.7 i0.6 i0.5 i0.4 i0.3 i0.2 i0.1 i0.0 default xxxxxxxx table 6. input port 1 register (address 01h) bit 7 6 5 4 3 2 1 0 symbol i1.7 i1.6 i1.5 i1.4 i1.3 i1.2 i1.1 i1.0 default xxxxxxxx table 7. output port 0 register (address 02h) bit 7 6 5 4 3 2 1 0 symbol o0.7 o0.6 o0.5 o0.4 o0.3 o0.2 o0.1 o0.0 default 11111111 table 8. output port 1 register (address 03h) bit 7 6 5 4 3 2 1 0 symbol o1.7 o1.6 o1.5 o1.4 o1.3 o1.2 o1.1 o1.0 default 11111111
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 7 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 6.2.4 polarity inversion register pair (04h, 05h) the polarity inversion registers (registers 4 and 5) allow polarity inversion of pins defined as inputs by the configuration register. if a bit in these registers is set (written with ?1?), the corresponding port pin?s polarity is inverted in the input register. if a bit in this register is cleared (written with a ?0?), the corresponding po rt pin?s polarity is retained. a register pair write is described in section 7.1 and a register pair read is described in section 7.2 . 6.2.5 configuration register pair (06h, 07h) the configuration registers (registers 6 and 7) configure the direction of the i/o pins. if a bit in these registers is set to 1, the corresponding port pin is enabled as a high-impedance input. if a bit in these registers is cleared to 0, the corresponding port pin is enabled as an output. a register pair write is described in section 7.1 and a register pair read is described in section 7.2 . table 9. polarity inversion port 0 register (address 04h) bit 7 6 5 4 3 2 1 0 symbol n0.7 n0.6 n0.5 n0.4 n0.3 n0.2 n0.1 n0.0 default 00000000 table 10. polarity inversion port 1 register (address 05h) bit 7 6 5 4 3 2 1 0 symbol n1.7 n1.6 n1.5 n1.4 n1.3 n1.2 n1.1 n1.0 default 00000000 table 11. configuration port 0 register (address 06h) bit 7 6 5 4 3 2 1 0 symbol c0.7 c0.6 c0.5 c0.4 c0.3 c0.2 c0.1 c0.0 default 11111111 table 12. configuration port 1 register (address 07h) bit 7 6 5 4 3 2 1 0 symbol c1.7 c1.6 c1.5 c1.4 c1.3 c1.2 c1.1 c1.0 default 11111111
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 8 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 6.3 i/o port when an i/o is configured as an input, fets q1 and q2 are off, which creates a high-impedance input. the input voltage may be raised above v dd to a maximum of 5.5 v. if the i/o is configured as an output, q1 or q2 is enabled, depending on the state of the output port register. in this case, there are low-impedance paths between the i/o pin and either v dd or v ss . the external voltage applied to th is i/o pin should not exceed the recommended levels for proper operation. at power-on reset, all registers return to default values. fig 6. simplified schematic of the i/os (p0_0 to p0_7, p1_0 to p1_7) v dd p0_0 to p0_7 p1_0 to p1_7 output port register data configuration register dq ck q data from shift register write configuration pulse output port register dq ck write pulse polarity inversion register dq ck data from shift register write polarity pulse input port register dq ck read pulse input port register data polarity inversion register data 002aah246 ff data from shift register ff ff ff q1 q2 v ss to int esd protection diode
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 9 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 6.4 power-on reset when power (from 0 v) is applied to v dd , an internal power-on reset holds the pca9535a in a reset condition until v dd has reached v por . at that time, the reset condition is released and the pca9535a registers and i 2 c-bus/smbus state machine initializes to their default states. after that, v dd must be lowered to below v porf and back up to the operating voltage for a power-reset cycle. see section 8.2 ? power-on reset requirements ? . 6.5 interrupt output an interrupt is generated by any rising or falling edge of the port inputs in the input mode. after time t v(int) , the signal int is valid. the interrupt is reset when data on the port changes back to the original value or when data is read form the port that generated the interrupt (see figure 10 and figure 11 ). resetting occurs in the read mode at the acknowledge (ack) or not acknowledge (nack) bit after the rising edge of the scl signal. interrupts that occur during the ack or nack clock pulse can be lost (or be very short) due to the resetting of the interrupt du ring this pulse. any change of the i/os after resetting is detected and is transmitted as int . a pin configured as an output cannot cause an interrupt. changing an i/o from an output to an input may cause a false interrupt to occu r, if the state of the pin does not match the contents of the input port register. 7. bus transactions the pca9535a is an i 2 c-bus slave device. data is exchanged between the master and pca9535a through write and read commands using i 2 c-bus. the two communication lines are a serial data line (sda) and a serial clock line (scl). both lines must be connected to a positive supply via a pull-up re sistor when connected to the output stages of a device. data transfer may be initiated only when the bus is not busy. 7.1 writing to the port registers data is transmitted to the pca9535a by sending the device address and setting the least significant bit to a logic 0 (see figure 4 ? pca9535a device address ? ). the command byte is sent after the address an d determines which register will receive the data following the command byte. eight registers within the pca9535a are configur ed to operate as four register pairs. the four pairs are input port, output port, polarity inversion, configuration registers. after sending data to one register, the next data byte is sent to the other register in the pair (see figure 7 and figure 8 ). for example, if the first byte is sent to output port 1 (register 3), the next byte is stored in output port 0 (register 2). there is no limitation on the number of data bytes sent in one write transmission. in this way, the host can continuously update a register pair independently of the other registers, or the host can simply update a single register.
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 10 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt fig 7. write to output port registers 1 0 0 a2 a1 a0 0 a s0 start condition r/w acknowledge from slave 002aah372 a scl sda a write to port data out from port 0 p t v(q) 987654321 command byte data to port 0 data 0 slave address 0000010 0 stop condition 0.0 0.7 acknowledge from slave acknowledge from slave data to port 1 data 1 1.0 1.7 a data out from port 1 t v(q) data valid fig 8. write to control registers 0 a s slave address start condition r/w acknowledge from slave 002aah373 0/1 0 0 0/1 0/1 0/1 0/1 0 command byte a acknowledge from slave 12345678 scl 9 sda data 0 a acknowledge from slave data to register 1 0 0 a2 a1 a0 0 p stop condition msb lsb a acknowledge from slave data 1 data to register msb lsb
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 11 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 7.2 reading the port registers in order to read data from the pca9535a, the bus master must first send the pca9535a address with the least significant bit set to a logic 0 (see figure 4 ? pca9535a device address ? ). the command byte is sent after the address and determines which register will be accessed. after a restart, th e device address is sent again, but this time the least significant bit is set to a logic 1. data from the register defined by the command byte is sent by the pca9535a (see figure 9 , figure 10 and figure 11 ). data is clocked into the register on the falling edge of the acknowledge clock pulse. after the first byte is read, additional bytes may be read but the data now reflects the information in the other register in the pair. for example, if input port 1 is read, the next byte read is input port 0. there is no limit on the number of data bytes received in one read transmission, but on the final byte received the bus master must not acknowledge the data. after a subsequent restart, the command byte contains the value of the next register to be read in the pair. for example, if input port 1 wa s read last before the restart, the register that is read after the restart is the input port 0. remark: transfer can be stopped at any time by a stop condition. fig 9. read from register a s start condition r/w acknowledge from slave 002aah374 a acknowledge from slave sda a p acknowledge from master data (first byte) slave address stop condition s (repeated) start condition (cont.) (cont.) 1 0 0 a2 a1 a0 1 a 0 r/w acknowledge from slave slave address at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter na no acknowledge from master 1 0 0 a2 a1 a0 0 0 data from lower or upper byte of register lsb msb data (last byte) data from upper or lower byte of register lsb msb 0/1 0 0 0/1 0/1 0/1 0/1 0 command byte
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 12 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt remark: transfer of data can be stopped at any moment by a stop condi tion. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). this figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data trans fer from p port (see figure 9 ). fig 10. read input port register, scenario 1 1 0 0 a2 a1 a0 1 a s0 start condition r/w acknowledge from slave 002aah375 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int 6543210 7 6543210 7 6543210 7 6543210 7 int t v(int) t rst(int)
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 13 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt remark: transfer of data can be stopped at any moment by a stop condi tion. when this occurs, data present at the latest acknowledge pha se is valid (output mode). it is assumed that the command byte has previously been set to ?00? (read input port register). this figure eliminates the command byte transfer and a restart between the initial slave address call and the actual data trans fer from p port (see figure 9 ). fig 11. read input port register, scenario 2 1 0 0 a2 a1 a0 1 a s0 start condition r/w acknowledge from slave 002aah376 a scl sda a read from port 0 p 987654321 i0.x slave address stop condition acknowledge from master a i1.x acknowledge from master a i0.x acknowledge from master 1 i1.x non acknowledge from master data into port 0 read from port 1 data into port 1 int t v(int) t rst(int) data 00 data 10 data 03 data 12 data 00 data 01 t h(d) t h(d) data 02 t su(d) data 03 t su(d) data 10 data 11 data 12
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 14 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 8. application design-in information 8.1 minimizing i dd when the i/os are used to control leds when the i/os are used to control leds, they are normally connected to v dd through a resistor as shown in figure 12 . since the led acts as a diode, when the led is off the i/o v i is about 1.2 v less than v dd . the supply current, i dd , increases as v i becomes lower than v dd . designs needing to minimize current consumpt ion, such as battery power applications, should consider maintaining the i/o pins greater than or equal to v dd when the led is off. figure 13 shows a high value resistor in parallel with the led. figure 14 shows v dd less than the led supply voltage by at least 1.2 v. both of these methods maintain the i/o v i at or above v dd and prevents additional supply current consumption when the led is off. device address configured as 0100 000x for this example. p0_0, p0_2, p0_3 configured as outputs. p0_1, p0_4, p0_5 configured as inputs. p0_6, p0_7 and (p1_0 to p1_7) configured as inputs. (1) external resistors are required for inputs (on p port) that ma y float. if a driver to an input will never let the input float , a resistor is not needed. if an output in the p port is configured as a push -pull output there is no need for external pull-up resistors. i f an output in the p port is configured as an open-drai n output, external pull-up resistors are required. fig 12. typical application pca9535a p0_0 p0_1 scl sda v dd (3.3 v) master controller scl sda int p0_2 v dd a1 a0 v dd v ss int 10 k sub-system 1 (1) (e.g., temp sensor) p0_3 int sub-system 2 (e.g., counter) reset controlled switch (e.g., cbt device) v dd a b enable sub-system 3 (1) (e.g., alarm system) alarm p0_4 p0_5 p0_6 10 digit numeric keypad v ss 002aag212 10 k 10 k 2 k 100 k (3) p0_7 p1_0 p1_1 p1_2 p1_3 p1_4 p1_5 p1_6 p1_7 a2
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 15 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 8.2 power-on reset requirements in the event of a glitch or data corruption, pca9535a can be reset to its default conditions by using the power-on reset feature. power-on reset requires that the device go through a power cycle to be complete ly reset. this reset also happens when the device is powered on for the first time in an application. the two types of power-on reset are shown in figure 15 and figure 16 . ta b l e 1 3 specifies the performance of the power-on reset feature for pca9535a for both types of power-on reset. fig 13. high value resistor in parallel with the led fig 14. device supplied by a lower voltage 002aag164 led v dd pn 100 k v dd 002aag165 led v dd pn 3.3 v 5 v fig 15. v dd is lowered below 0.2 v or to 0 v and then ramped up to v dd fig 16. v dd is lowered below the por threshold, then ramped back up to v dd 002aah329 v dd time ramp-up ramp-down (dv/dt) r (dv/dt) f re-ramp-up (dv/dt) r time to re-ramp when v dd drops below 0.2 v or to v ss t d(rst) 002aah330 v dd time ramp-down (dv/dt) f ramp-up (dv/dt) r time to re-ramp when v dd drops to v por(min) ? 50 mv t d(rst) v i drops below por levels
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 16 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt [1] level that v dd can glitch down to with a ramp rate of 0.4 ? s/v, but not cause a functional disruption when t w(gl)vdd <1 ? s. [2] glitch width that will not cause a functional disruption when ? v dd(gl) =0.5 ? v dd . glitches in the power supply can also affect the power-on reset performance of this device. the glitch width (t w(gl)vdd ) and glitch height ( ? v dd(gl) ) are dependent on each other. the bypass capacitance, source impedan ce, and device impedance are factors that affect power-on reset performance. figure 17 and ta b l e 1 3 provide more information on how to measure thes e specifications. v por is critical to the power-on reset. v por is the voltage level at which the reset condition is released and all the registers and the i 2 c-bus/smbus state machine are initialized to their default states. the value of v por differs based on the v dd being lowered to or from 0v. figure 18 and ta b l e 1 3 provide more details on this specification. table 13. recommended supply sequencing and ramp rates t amb =25 ? c (unless otherwise noted). not tested; specified by design. symbol parameter condition min typ max unit (dv/dt) f fall rate of change of voltage figure 15 0.1 - 2000 ms (dv/dt) r rise rate of change of voltage figure 15 0.1 - 2000 ms t d(rst) reset delay time figure 15 ; re-ramp time when v dd drops below 0.2 v or to v ss 1- - ? s figure 16 ; re-ramp time when v dd drops to v por(min) ? 50 mv 1- - ? s ? v dd(gl) glitch supply voltage difference figure 17 [1] --1v t w(gl)vdd supply voltage glitch pulse width figure 17 [2] --10 ? s v por(trip) power-on reset trip voltage falling v dd 0.7 - - v rising v dd --1.4v fig 17. glitch width and glitch height fig 18. power-on reset voltage (v por ) 002aah331 v dd time t w(gl)vdd ?v dd(gl) 002aah332 por time v dd time v por (rising v dd ) v por (falling v dd )
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 17 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 9. limiting values [1] the input negative-voltage and output voltage ratings may be exceeded if the input and output current ratings are observed. 10. recommended operating conditions 11. thermal characteristics [1] the package thermal impedance is calc ulated in accordance with jesd 51-7. table 14. limiting values in accordance with the absolute ma ximum rating system (iec 60134). symbol parameter conditions min max unit v dd supply voltage ? 0.5 +6.5 v v i input voltage [1] ? 0.5 +6.5 v v o output voltage [1] ? 0.5 +6.5 v i ik input clamping current a0, a1, a2, scl; v i <0v - ? 20 ma i ok output clamping current int ; v o <0v - ? 20 ma i iok input/output clamping current p port; v o <0v or v o >v dd - ? 20 ma sda; v o <0v or v o >v dd - ? 20 ma i ol low-level output current continuous; i/o port - 50 ma continuous; sda, int -25ma i oh high-level output current continuous; p port - 25 ma i dd supply current - 160 ma i ss ground supply current - 200 ma p tot total power dissipation - 200 mw t stg storage temperature ? 65 +150 ?c t j(max) maximum junction temperature - 125 ?c table 15. operating conditions symbol parameter conditions min max unit v dd supply voltage 1.65 5.5 v v ih high-level input voltage scl, sda 0.7 ? v dd 5.5 v a0, a1, a2, p1_7 to p0_0 0.7 ? v dd 5.5 v v il low-level input voltage scl, sda ? 0.5 0.3 ? v dd v a0, a1, a2, p1_7 to p0_0 ? 0.5 0.3 ? v dd v i oh high-level output current p1_7 to p0_0 - 10 ma i ol low-level output current p1_7 to p0_0 - 25 ma t amb ambient temperature operating in free air ? 40 +85 ?c table 16. thermal characteristics symbol parameter conditions max unit z th(j-a) transient thermal impedance from junction to ambient tssop24 package [1] 88 k/w hwqfn24 package [1] 66 k/w
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 18 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 12. static characteristics table 17. static characteristics t amb = ? 40 ? c to +85 ? c; v dd = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit v ik input clamping voltage i i = ? 18 ma ? 1.2--v v por power-on reset voltage v i =v dd or v ss ; i o =0ma - 1.1 1.4 v i ol low-level output current v ol = 0.4 v; v dd = 1.65 v to 5.5 v sda 3--ma int 315 [2] -ma p port v ol = 0.5 v; v dd =1.65v [3] 810- ma v ol = 0.7 v; v dd =1.65v [3] 10 13 - ma v ol = 0.5 v; v dd =2.3v [3] 810- ma v ol = 0.7 v; v dd =2.3v [3] 10 13 - ma v ol = 0.5 v; v dd =3.0v [3] 814- ma v ol = 0.7 v; v dd =3.0v [3] 10 19 - ma v ol = 0.5 v; v dd =4.5v [3] 817- ma v ol = 0.7 v; v dd =4.5v [3] 10 24 - ma v oh high-level output voltage p port i oh = ? 8ma; v dd =1.65v [4] 1.2--v i oh = ? 10 ma; v dd =1.65v [4] 1.1--v i oh = ? 8ma; v dd =2.3v [4] 1.8--v i oh = ? 10 ma; v dd =2.3v [4] 1.7--v i oh = ? 8ma; v dd =3.0v [4] 2.6--v i oh = ? 10 ma; v dd =3.0v [4] 2.5--v i oh = ? 8ma; v dd =4.5v [4] 4.1--v i oh = ? 10 ma; v dd =4.5v [4] 4.0--v v ol low-level output voltage p port; i ol =8ma v dd =1.65v --0.45v v dd =2.3v --0.25v v dd =3.0v --0.25v v dd =4.5v --0.2v i i input current v dd =1.65v to 5.5v scl, sda; v i =v dd or v ss --? 1 ? a a0, a1, a2; v i =v dd or v ss --? 1 ? a i ih high-level input current p port; v i =v dd ; v dd =1.65v to 5.5v - - 1 ? a i il low-level input current p port; v i =v ss ; v dd = 1.65 v to 5.5 v - - 1 ? a
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 19 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt [1] for i dd , all typical values are at nominal supply voltage (1.8 v, 2.5 v, 3.3 v, 3.6 v or 5 v v dd ) and t amb =25 ? c. except for i dd , the typical values are at v dd = 3.3 v and t amb =25 ? c. [2] typical value for t amb =25 ? c. v ol = 0.4 v and v dd = 3.3 v. typical value for v dd <2.5v, v ol =0.6v. [3] each i/o must be externally limited to a maximum of 25 ma and the device must be limited to a maximum current of 200 ma. [4] the total current sourced by all i/os must be limited to 160 ma. i dd supply current sda, p port, a0, a1, a2; v i on sda = v dd or v ss ; v i on p port and a0, a1, a2 = v dd ; i o =0ma;i/o=inputs; f scl = 400 khz v dd = 3.6 v to 5.5 v - 10 25 ? a v dd = 2.3 v to 3.6 v - 6.5 15 ? a v dd = 1.65 v to 2.3 v - 4 9 ? a scl, sda, p port, a0, a1, a2; v i on scl, sda = v dd or v ss ; v i on p port and a0, a1, a2 = v dd ; i o =0ma;i/o=inputs; f scl = 0 khz v dd = 3.6 v to 5.5 v - 1.5 7 ? a v dd = 2.3 v to 3.6 v - 1 3.2 ? a v dd = 1.65 v to 2.3 v - 0.5 1.7 ? a active mode; p port, a0, a1, a2; v i on p port, a0, a1, a2 = v dd ; i o = 0 ma; i/o = inputs; f scl = 400 khz, continuous register read v dd = 3.6 v to 5.5 v - 60 125 ? a v dd = 2.3 v to 3.6 v - 40 75 ? a v dd = 1.65 v to 2.3 v - 20 45 ? a ? i dd additional quiescent supply current scl, sda; one input at v dd ? 0.6 v, other inputs at v dd or v ss ; v dd = 1.65 v to 5.5 v --25 ? a p port, a0, a1, a2; one input at v dd ? 0.6 v, other inputs at v dd or v ss ; v dd =1.65vto5.5v --80 ? a c i input capacitance v i =v dd or v ss ; v dd =1.65vto5.5v - 6 7 pf c io input/output capacitance v i/o =v dd or v ss ; v dd =1.65vto5.5v - 7 8 pf v i/o =v dd or v ss ; v dd =1.65vto5.5v - 7.5 8.5 pf table 17. static characteristics ?continued t amb = ? 40 ? c to +85 ? c; v dd = 1.65 v to 5.5 v; unless otherwise specified. symbol parameter conditions min typ [1] max unit
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 20 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 12.1 typical characteristics fig 19. supply current versus ambient temperature fig 20. standby supply current versus ambient temperature t amb =25 ? c fig 21. supply current versus supply voltage 8 12 4 16 20 i dd (a) 0 t amb (c) ?40 85 60 10 35 ?15 002aah333 v dd = 5.5 v 5.0 v 3.6 v 3.3 v 2.5 v 2.3 v v dd = 1.8 v 1.65 v 600 800 400 1400 i dd(stb) (na) 0 t amb (c) ?40 85 60 10 35 ?15 002aah334 v dd = 5.5 v 5.0 v 3.6 v 3.3 v 200 1000 2.5 v 2.3 v 1.8 v 1.65 v 8 12 4 16 20 i dd (a) 0 v dd (v) 1.5 5.5 4.5 2.5 3.5 002aah335
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 21 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt a. v dd =1.65v b. v dd =1.8v c. v dd =2.5v d. v dd =3.3v e. v dd =5.0v f. v dd =5.5v fig 22. i/o sink current versus low-level output voltage v ol (v) 0 0.3 0.2 0.1 002aaf578 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf579 15 25 35 i sink (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v ol (v) 0 0.3 0.2 0.1 002aaf580 20 50 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 30 40 v ol (v) 0 0.3 0.2 0.1 002aaf581 20 40 60 i sink (ma) 0 t amb = ?40 c 25 c 85 c v ol (v) 0 0.3 0.2 0.1 002aaf582 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v ol (v) 0 0.3 0.2 0.1 002aaf583 30 50 70 i sink (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 22 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt a. v dd =1.65v b. v dd =1.8v c. v dd =2.5v d. v dd =3.3v e. v dd =5.0v f. v dd =5.5v fig 23. i/o source current versus high-level output voltage v dd ? v oh (v) 0 0.6 0.4 0.2 002aah110 10 20 30 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah111 15 25 35 i source (ma) 0 t amb = ?40 c 25 c 85 c 5 10 20 30 v dd ? v oh (v) 0 0.6 0.4 0.2 002aah112 20 40 60 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah113 30 50 70 i source (ma) 0 t amb = ?40 c 25 c 85 c 10 20 40 60 v dd ? v oh (v) 0 0.6 0.4 0.2 002aah114 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c v dd ? v oh (v) 0 0.6 0.4 0.2 002aah115 30 60 90 i source (ma) 0 t amb = ?40 c 25 c 85 c
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 23 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt (1) v dd = 1.8 v; i sink =10ma (2) v dd = 5 v; i sink =10ma (3) v dd = 1.8 v; i sink =1ma (4) v dd = 5 v; i sink =1ma i source = ? 10 ma fig 24. low-level output voltage versus temperature fig 25. i/o high voltage versus temperature 60 80 20 100 120 v ol (mv) 0 t amb (c) ?40 85 60 10 35 ?15 002aah056 (1) (3) (4) (2) 40 t amb (c) ?40 85 60 10 35 ?15 002aah343 160 120 200 0 v dd ? v oh (mv) v dd = 1.8 v 5 v 80 40
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 24 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 13. dynamic characteristics table 18. i 2 c-bus interface timing requirements over recommended operating free air temperat ure range, unless otherwise specified. see figure 26 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max f scl scl clock frequency 0 100 0 400 khz t high high period of the scl clock 4 - 0.6 - ? s t low low period of the scl clock 4.7 - 1.3 - ? s t sp pulse width of spikes that must be suppressed by the input filter 050 0 50ns t su;dat data set-up time 250 - 100 - ns t hd;dat data hold time 0 - 0 - ns t r rise time of both sda and scl signals - 1000 20 300 ns t f fall time of both sda and scl signals - 300 20 ? (v dd /5.5v) 300 ns t buf bus free time between a stop and start condition 4.7 - 1.3 - ? s t su;sta set-up time for a repeated start condition 4.7 - 0.6 - ? s t hd;sta hold time (repeated) start condition 4 - 0.6 - ? s t su;sto set-up time for stop condition 4 - 0.6 - ? s t vd;dat data valid time scl low to sda output valid -3.45 - 0.9 ? s t vd;ack data valid acknowledge time ack signal from scl low to sda (out) low -3.45 - 0.9 ? s table 19. switching characteristics over recommended operating free air temperature range; c l ? 100 pf; unless other wise specified. see figure 27 . symbol parameter conditions standard-mode i 2 c-bus fast-mode i 2 c-bus unit min max min max t v(int) valid time on pin int from p port to int -1-1 ? s t rst(int) reset time on pin int from scl to int -1-1 ? s t v(q) data output valid time from scl to p port - 400 - 400 ns t su(d) data input set-up time from p port to scl 0 - 0 - ns t h(d) data input hold time from p port to scl 300 - 300 - ns
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 25 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 14. parameter measure ment information a. sda load configuration b. transaction format c. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. byte 1 = i 2 c-bus address; byte 2, byte 3 = p port data. (1) see figure 9 . fig 26. i 2 c-bus interface load circuit and voltage waveforms 002aag803 dut c l = 50 pf r l = 1 k sda v dd stop condition (p) data bit 0 (lsb) data bit 7 (msb) ack (a) r/w bit 0 (lsb) address bit 1 address bit 7 (msb) start condition (s) stop condition (p) two bytes for read input port register (1) 002aag952 t low t high t r t f 0.7 v dd 0.3 v dd 0.7 v dd 0.3 v dd t sp t buf t f t hd;sta t r scl sda t su;dat t hd;dat t f(o) t vd;ack t vd;dat t vd;ack t su;sta t su;sto 002aag804 repeat start condition stop condition
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 26 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt a. interrupt load configuration b. voltage waveforms c l includes probe and jig capacitance. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. all parameters and waveforms ar e not applicable to all devices. fig 27. interrupt load circuit and voltage waveforms 002aah069 dut c l = 100 pf r l = 4.7 k int v dd 1101a1a01 a s1 slave address start condition r/w acknowledge from slave 002aah070 8 bits (one data byte) from port a acknowledge from slave sda 1 no acknowledge from master data into port data from port data 1 data 2 int data 2 data 1 p stop condition t v(int) t rst(int) t su(d) 12345678 scl 9 address t rst(int) a a view a - a int pn t v(int) 0.5 v dd 0.5 v dd view b - b scl 0.5 v dd int r/w a t rst(int) 0.3 v dd 0.7 v dd b b
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 27 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt a. p port load configuration b. write mode (r/w =0) c. read mode (r/w =1) c l includes probe and jig capacitance. t v(q) is measured from 0.7 ? v dd on scl to 50 % i/o (pn) output. all inputs are supplied by generators havi ng the following characteristics: prr ? 10 mhz; z o =50 ? ; t r /t f ? 30 ns. the outputs are measured one at a time, with one transition per measurement. all parameters and waveforms ar e not applicable to all devices. fig 28. p port load circuit and voltage waveforms 002aag805 dut c l = 50 pf 500 pn 2 v dd 500 002aag806 scl sda p0 a t v(q) 0.3 v dd 0.7 v dd p7 last stable bit unstable data pn 002aag807 scl pn p0 a t h(d) 0.3 v dd 0.7 v dd p7 t su(d)
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 28 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 15. package outline fig 29. package outline sot355-1 (tssop24) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 7.9 7.7 4.5 4.3 0.65 6.6 6.2 0.4 0.3 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot355-1 mo-153 99-12-27 03-02-19 0.25 0.5 0.2 w m b p z e 11 2 24 13 pin 1 index a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a d y 0 2.5 5 mm scale tssop24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm sot355-1 a max. 1.1
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 29 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt fig 30. package outline sot994-1 (hwqfn24) references outline version european projection issue date iec jedec jeita sot994-1 - - - mo-220 - - - sot994-1 07-02-07 07-03-03 note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. unit a (1) max mm 0.8 0.05 0.00 0.30 0.18 4.1 3.9 2.25 1.95 4.1 3.9 2.25 1.95 2.5 2.5 0.1 a 1 dimensions (mm are the original dimensions) hwqfn24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm 0 2.5 5 mm scale b c 0.2 d (1) d h e (1) e h e 0.5 e 1 e 2 l 0.5 0.3 v w 0.05 y 0.05 y 1 0.1 b a terminal 1 index area e d detail x a a 1 c b e 2 e 1 e e 1/2 e 1/2 e ac b ? v m c ? w m terminal 1 index area 6 13 12 7 18 24 19 1 l e h d h c y c y 1 x
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 30 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 16. handling information all input and output pins are protected ag ainst electrostatic discharge (esd) under normal handling. when handling ensure that the appropriate precautions are taken as described in jesd625-a or equivalent standards. 17. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 17.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 17.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 17.3 wave soldering key characteristics in wave soldering are:
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 31 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities 17.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 31 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 0 and 21 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 31 . table 20. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 21. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 32 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . msl: moisture sensitivity level fig 31. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 33 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 18. soldering: pcb footprints fig 32. pcb footprint for sot355-1 (tssop24); reflow soldering dimensions in mm ay by d1 d2 gy hy p1 c gx sot355-1_fr hx sot355-1 solder land occupied area footprint information for reflow soldering of tssop24 package ay by gy c hy hx gx p1 generic footprint pattern refer to the package outline drawing for actual layout p2 (0.125) (0.125) d1 d2 (4x) p2 7.200 4.500 1.350 0.400 0.600 8.200 5.300 7.450 8.600 0.650 0.750
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 34 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt fig 33. pcb footprint for sot994-1 (hwqfn24); reflow soldering sot994-1 footprint information for reflow soldering of hvqfn24 package dimensions in mm ax ay bx by d slx sly spx tot spy tot spx spy gx gy hx hy 5.000 5.000 3.200 3.200 p 0.500 0.240 c 0.900 2.100 2.100 1.200 1.200 0.450 0.450 4.300 4.300 5.250 5.250 nspx nspy 22 sot994-1_fr occupied area ax bx slx gx gy hy hx aybysly p 0.025 0.025 d (0.105) spx tot spy tot nspx nspy spx spy solder land plus solder paste solder land solder paste deposit c generic footprint pattern refer to the package outline drawing for actual layout issue date 07-09-24 09-06-15
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 35 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 19. abbreviations 20. revision history table 22. abbreviations acronym description acpi advanced configuration and power interface cbt cross-bar technology cdm charged-device model cmos complementary metal-oxide semiconductor esd electrostatic discharge fet field-effect transistor ff flip-flop gpio general purpose input/output hbm human body model i 2 c-bus inter-integrated circuit bus i/o input/output led light emitting diode pcb printed-circuit board por power-on reset smbus system management bus table 23. revision history document id release date data sheet status change notice supersedes pca9535a v.1 20120911 product data sheet - -
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 36 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt 21. legal information 21.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 21.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 21.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such info rmation. nxp semiconductors takes no responsibility for the content in this document if provided by an information source outside of nxp semiconductors. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors and its suppliers accept no liability for inclusion and/or use of nxp semiconducto rs products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
pca9535a all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2012. all rights reserved. product data sheet rev. 1 ? 11 september 2012 37 of 38 nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 21.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 22. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors pca9535a low-voltage 16-bit i 2 c-bus i/o port with interrupt ? nxp b.v. 2012. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 11 september 2012 document identifier: pca9535a please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 23. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 5 6.1 device address . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2.1 pointer register and command byte . . . . . . . . . 5 6.2.2 input port regist er pair (00h, 01h) . . . . . . . . . . . 6 6.2.3 output port register pair (02h, 03h) . . . . . . . . . 6 6.2.4 polarity inversion register pair (04h, 05h) . . . . . 7 6.2.5 configuration register pair (06h, 07h) . . . . . . . . 7 6.3 i/o port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6.4 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 9 6.5 interrupt output . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9 7.1 writing to the port registers. . . . . . . . . . . . . . . . 9 7.2 reading the port registers . . . . . . . . . . . . . . . 11 8 application design-in information . . . . . . . . . 14 8.1 minimizing i dd when the i/os are used to control leds . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.2 power-on reset requirements . . . . . . . . . . . . . 15 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 10 recommended operating conditions. . . . . . . 17 11 thermal characteristics . . . . . . . . . . . . . . . . . 17 12 static characteristics. . . . . . . . . . . . . . . . . . . . 18 12.1 typical characteristics . . . . . . . . . . . . . . . . . . 20 13 dynamic characteristics . . . . . . . . . . . . . . . . . 24 14 parameter measurement information . . . . . . 25 15 package outline . . . . . . . . . . . . . . . . . . . . . . . . 28 16 handling information. . . . . . . . . . . . . . . . . . . . 30 17 soldering of smd packages . . . . . . . . . . . . . . 30 17.1 introduction to soldering . . . . . . . . . . . . . . . . . 30 17.2 wave and reflow soldering . . . . . . . . . . . . . . . 30 17.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 30 17.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 31 18 soldering: pcb footprints. . . . . . . . . . . . . . . . 33 19 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 35 20 revision history . . . . . . . . . . . . . . . . . . . . . . . . 35 21 legal information. . . . . . . . . . . . . . . . . . . . . . . 36 21.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 36 21.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 21.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 36 21.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 37 22 contact information . . . . . . . . . . . . . . . . . . . . 37 23 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

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